1. Field of the Invention
The present invention relates to a DRAM (Dynamic Random Access Memory) and access method thereof, and more particularly to a DRAM incorporating an access method for achieving a high data rate in random row access.
2. Background of the Invention
The relatively slower speed of DRAM arrays as compared to the processor represents the major performance limiting factor in microprocessor based systems. Particularly in the case of random row access where the row address changes continuously. The operational latency associated with random row access and the additional delay introduced with precharge for the previous access cause the performance of DRAM to lag behind the processor. In order to mitigate the degraded performance associated with random row access as much as possible, recent high-performance DRAM's such as SDRAM (synchronous DRAM), SDRAM DDR (SDRAM Double Data Rate), Rambus, etc., employ multiple bank array topology. Furthermore, for speeding up DRAM, every effort is made to incorporate a system program or memory mapping scheme such that a column address in the same page can be accessed.
However, this is not possible between individual programs and consequently an access to another row address is bound to occur. Given that the banks are provided, an access to the next row address selected can occur without precharging the row currently accessed if the next row address is in a different bank than the one currently accessed. Therefore, the next burst takes place just when the previous burst ends, which allows the fast processing without temporal empty periods on the data bus.
In order to migrate from one bank to another without bank conflicts, it is necessary to increase the number of banks considerably. An active, precharge as well as read and write signals and control for these signals for each bank are required. Since provision of a number of banks brings an increase of chip size, realistically only four banks are usually able to be provided for SDRAM.
For example, the Rambus DRAM, provides 16 banks of 72 Mb each or 32 banks of 144 Mb each with a correspondingly large penalty in chip area. The cycle time is considerably longer for this configuration and three banks are occupied for one row access because banks are configured across shared sense amplifiers. Thus, there will be a small gain in performance even if the number of banks is increased to 32 while consuming still more chip area. The limitations of the Rambus implementation, which are not atypical, suggest that a high data rate for random row access is not possible.
As shown in FIG. 1, a conventional SDRAM 40 has four banks of 32 Mb each, which are independent blocks. One row access activates 8-K sense amplifiers. One bit line is traversed by 512 word lines orthogonally. Therefore, this means that a block comprised of a cell array of 4 Mb (=512×8 K) is activated. Namely, a 32 Mb bank is comprised of 8 blocks. According to the design, other row addresses in the same bank can not be accessed.
Practically speaking, row addresses that can not be accessed without incurring additional delay comprise the 511 other word lines in the same 4 Mb bank. The word lines of the other seven blocks that do not share sense amplifiers are realistically accessible even in the same bank. Nevertheless, the reason for not designating this block unit as a discrete bank is because chip size increases significantly with the number of banks. This is primarily due to the added complexity associated with additional control logic and signal lines as the number of banks increases. Since 16 data lines from each bank are connected to 16 data I/O pads, the number of wire connections to I/O pads increases when the number of banks increases.
A Rambus DRAM architecture 42, is illustrated in FIG. 2, where banks are composed as a 4 Mb block surrounded by 512 word lines sharing sense amplifiers, wherein 32 banks are provided in a whole chip, which is more than a typical SDRAM design. In order to avoid wiring congestion, the Rambus array 42 is configured as a vertical stack structure as shown in FIG. 2. However, the increase of chip size is inevitable due to a large number of control signals to each bank. Furthermore, since the length of pages becomes shorter and the probability of page misses increases when increasing the number of banks, it is necessary to increase the number of banks to be activated.
Since the number of banks that can be used for a new row access decreases, resulting in the increase of probability of bank conflicts, the purpose of increasing the number of banks, that is, decreasing the number of bank conflicts, is defeated. Therefore, though the probability of bank conflicts is reduced by increasing the number of banks while maintaining most banks not activated, the page hit rate may actually decrease. In this regard, the expectation of a high hit rate in page mode while attempting to avoid bank conflicts is not realistic, thus the performance is not enhanced very much regardless of the number of banks. As a result, it is essentially impossible to solve the dual problems of page misses and bank conflicts simply by increasing the number of banks.
It is therefore an object of the present invention to provide a DRAM and access method for DRAM with a high data rate in a random row access.